
Summary of Project Flow:

1. Created parameterized BIST for all single port SRAM.

2. At present, it takes care of basic algorithms that captures basic 85-90% fault. Increasing further coverage requires complex algorithm implementation.

3. The BIST has been verified functionally by traversing the address space across whole memory and checked the corresponding data to be written and read.

4. TOP to Bottom methodology has been implemented

5. BIST has been placed as wrapper around memory and extra "tbist" pin/port has been added to Access/Bypass through BIST inputs.

6. Synthesis and P&R has been tried in 2 ways:
   - Synthesis of individual blocks (BIST for IC_RAM, BIST for IC_TAG & or1200_ic_fsm) has been done & placed them individually into the top by generating LEF of each. (Tedious process and not worth as I was not planning to keep those block on separate power domain, if power domain are separate for each block, it is worth to generate individual LEF and route them in top)

   - or1200_ic_top.v was consider as top module and all digital blocks instantiated has been synthesized from the top (as we consider all blocks in same power domain) with memories as hard macro. Later LEF to FRAM/CELL view conversion has been done to read the hard macro into IC Compiler.


Notes:

- ICC scripts has been updated/changed based on commands requires to incorporate the changes or optimize the design.

- Routing has been done at Global, Track & Detail level to further optimize the routing.

- Increased frequency up to 1Ghz to check the maximum frequency characterization for BIST and other digital blocks
